pipeline architecture

Design and implementation of FDDI adapter based on similar pipeline architecture

基于类流水线结构FDDI适配器的设计与实现

A Pipeline Architecture for High Speed FIR Filters

高速FIR滤波器的流水线结构

Research on Pipeline Architecture and Verification for Digital Signal Processor

数字信号处理器的流水结构设计及验证研究

A VLSI Design with Advanced Pipeline Architecture for Fuzzy Micro Controller

一种采用先进流水技术的模糊控制器VLSI结构

It is a very high speed VLSI Design through the pipeline architecture with power optimization .

该设计采用流水线处理结构，能达到非常快的处理速度，同时进行了功耗优化。

This paper proposes a two-level pipeline architecture for sub-pixel interpolation .

本论文提出了子像素插值的两层流水线设计方法。

KETA : A Novel Kernel Web Server with the Software Pipeline Architecture

基于软流水体系结构的内核Web服务器&KETA

Pipeline architecture can be an important tool in managing security issues from XML 's transparency .

管道架构在管理XML透明性所带来的问题时是一种重要的工具。

A voltage scaling A / D converter with improved pipeline architecture is presented in the paper .

文章介绍了流水线电压型结构A/D转换器的一种改进设计。

A specific VLSI design with advanced pipeline architecture for fuzzy micro controller is presented in this paper .

本文介绍了一种采用先进流水技术的模糊控制器（FMC）的VLSI结构。

A parallel pipeline architecture is proposed to implement the proposed method in System on Chip ( SoC ) .

同时提出了采用并行流水线结构进行该方法的在系统芯片（SoC）实现。

Building on pipeline architecture

以管道架构为基础进行构建

Improvement on CORDIC Pipeline Architecture in FFT Design

CORDIC流水线结构在FFT设计中的改进

Simulation results show that this kind of arithmetic coder with pipeline architecture can achieve a good coding speed .

实验表明，这种流水线结构的算术编码器能够获得较高的编码速度。

This structure used parallel pipeline architecture , each layer of wavelet transform processed by parallel while pixels processed by pipeline .

该模型采用流水线并行结构，即对图像中各行像素进行流水线处理的同时，对小波分解的各级采用并行结构处理。

A RISC instruction pipeline architecture

一种RISC型微处理器指令流水线结构

In deblocking filter module , according to analysis critical path of the filtering process , five-stage pipeline architecture is adopted to improve system performance .

针对去块效应滤波模块，首先对整个滤波过程进行了关键路径进行分析，提出了5级流水线架构。

The Pipeline architecture is employed to design the wavelet transform module , implement different layer of the wavelet decomposition in different module to improve operational efficiency .

小波变换模块采用流水线设计，即把各层小波变换分成各个模块独立实现，以提高运算效率。

XML pipeline architecture is the idea of effective XML data flow as a set of small , well-defined processing stages ( largely , transforms ) .

XML管道架构是将有效的XML数据流当成一系列定义良好、较小的处理阶段（主要是转换）的思想。

The design and implementation of FFT module in microwave relay based on FPGA is mainly presented . All-parallel pipeline architecture for FFT calculation is put forward .

主要介绍基于现场可编程门阵列（FPGA）的微波接力通信中FFT模块的设计与实现方案。

On the basis of Viterbi algorithm , a novel pipeline architecture of ACS module and a reasonable arrangement method of survive paths are present in this paper .

在分析Viterbi译码算法基础上，采用一种新的流水结构设计Viterbi译码器的ACS模块。

This paper presents an optimized architecture of a scalable radix-4 modular multiplier , based on radix-4 Montgomery multiplication algorithm and improved pipeline architecture .

基于基为4的Montgomery模乘算法和改进的流水线组织结构，文章提出了一种结构优化的可扩展模乘运算器结构。

Compared with the full parallel architecture , the memory cost of the designed processor decreases , thus the speed is higher than that of the SDF pipeline architecture .

该处理器内存资源消耗较并行结构有所减少，运算速度较单独的SDF流水线结构有所提高。

The AD9200 uses a multistage differential pipeline architecture at20 MSPS data rates and guarantees no missing codes over the full operating temperature range .

它采用多级差分流水线架构，数据速率达20MSPS，在整个工作温度范围内保证无失码。

To obtain the highest data reuse efficiency and minimum I / O pin count while achieving 100 % hardware efficiency , a systolic array and full pipeline architecture is adopted .

通过脉动阵列和全流水线的设计，达到最高的数据重用率、最小的I/O引脚数和100%的硬件计算效率。

Secondly , this paper designs and realizes a new multi-threads Web server in kernel - KETA ( KErnel neTwork gear ), basing the soft pipeline architecture in Kylin .

基于所提出的原则，本文提出了一种基于软流水体系结构的新型内核级多线程Web服务器体系结构&KETA（KErnelneTworkgeAr）。

The MQ-codec presented adopts a 3-stage pipeline architecture . Its speed is up to 1 bit / cycle . A good trade-off between speed and area is achieved .

采用3级流水线结构的MQ编解码器架构，编解码器的工作效率可以达到1bit/cycle，并且在速度与面积之间达到了很好的平衡。

A eleven stage pipeline architecture was used in this design : the preliminary ten stages 1.5 bit per-stage sub ADC , and the last stage is an 2 bit flash ADC .

设计中采用了十一级流水线模式的结构：前十级每级.5位flash子模数转换器，第十二级为2位flash子模数转换器的流水线结构，采用冗余矫正的方法进行数字矫正。

As parts of research work , this paper mainly concerns DSP 's pipeline architecture design , various hazards detection and elimination of pipelined DSP with heavily compressed instruction set , and comprehensive functional verification platform development .

本文作为部分研究成果，着重探讨了16位定点DSP处理器的流水结构设计，解决了采用深度压缩指令集的DSP处理器竞争检测和消除问题，和开发了功能仿真验证平台。

Based on modified multiple-word radix-4 Montgomery algorithm and improved pipeline architecture , an area efficient RSA crypto-processor is implemented , which supports scalable keys of length up to 2048 bits .

采用基于字运算的高基Montgomery模乘算法，并且应用了改进的流水线组织结构，以较小的硬件开销实现了一个密钥长度最高可达2048bits、速度面积比性能很高的RSA密码协处理器。